The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value. It is available to set the lock monitoring period and the lock detector accuracy (5.5...12 ns).
PLL lock detector with low current consumption and high accuracy
Overview
Key Features
- TSMC SiGe 0.18 um
- Low current consumption
- High accuracy
- Portable to other technologies (upon request)
Block Diagram
Applications
- Phase-locked loop synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC SiGe 0.18 um
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
180nm
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