PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Overview
Input 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.
Technical Specifications
Foundry, Node
UMC 65nm SP
UMC
Pre-Silicon:
65nm
SP
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