PLL (Frequency Synthesizer) IP, Input: 33MHz - 300MHz, Output: 1000MHz - 1500MHz, UMC 55nm SP process
Overview
Input 33M-300MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- 32KHz input frequency Synthesizer PLL
- PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process
- PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm SP process
- Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter - GlobalFoundries 55nm
- Fractional-N PLL Frequency Synthesizer on TSMC CLN40G