PLL (Frequency Synthesizer) IP, Input: 25MHz - 27MHz, Output: 1050MHz - 1070MHz, UMC 0.13um HS/FSG process
Overview
UMC 0.13um HS/FSG process PLL for DDR2. Clock input 25-27MHz, clock output 1050-1070MHz.
Technical Specifications
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm
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