PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 800MHz/1000MHz, 533MHz/666MHz, 400MHz/500MHz, 266MHz/533MHz, UMC 55nm SP process
Overview
Input 12MHz, output 800MHz/1000MHz, 533MHz/666MHz, 400MHz/500MHz, 266MHz/533MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
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