PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 55nm SP process
Overview
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 55nm SP Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
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