Phase Locked Loop (PLL) Frequency Synthesizer Core

Overview

For general purpose Phase Locked Loops (PLL), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: C3-PLL-2, an IP core for frequency synthesizer applications.
C3-PLL-2 relies on the DIGICC design concept of Cologne Chip, which makes it possible to be easily implemented in all process technologies as a fully digital circuitry. The lock time of the PLL is very low while the used circuit area is smaller than that of competing technologies. Because of its pure digital nature the C3-PLL-2 does neither require any additional pad or pin nor external or internal loop capacitors. External filters for the supply voltage are normally not needed. A patent is pending for this innovation of Cologne Chip.

C3-PLL-2 is based on C3-PLL-1 and contains additional read/write registers with address decoder, a predivider and a post-scaler.

Key Features

  • Fully digital - designed for use with standard cell libraries for digital logic
  • Implementable in any digital CMOS process technology
  • Typical oscillator frequency ranges:
    • 0.50 µm: 60-120 MHz
    • 0.35 µm: 100-200 MHz
    • 0.25 µm: 140-280 MHz
    • 0.18 µm: 160-320 MHz
    • 0.13 µm: 180-360 MHz
      • 90 nm: 200-400 MHz
    • Frequency multiplication range: 5 to 255
    • Predivider and post-scaler with divider range 1..256 each
    • Jitter similar to analog PLLs
    • No pads, special pins, external loop filter capacity or supply voltage filters needed
    • Very fast lock time (worst case 2,000 reference clocks)
    • Stand-by mode (oscillator stopped but center frequency preserved) >> super-fast lock time when returning from stand-by mode (only some clock cycles)
    • Stand-by also reduces power to zero (only leakage current)
    • Very small area (< 3,000 gates)

    Benefits

    • Fully digital
    • Implementable in any digital CMOS process technology
    • No pads, special pins or external loop filter capacity or supply voltage filters needed

    Deliverables

    • Compiled netlist for destination technology and test vectors.

    Technical Specifications

    Availability
    Available
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Semiconductor IP