The Mentor Graphics PCMCIA core provides PCMCIA card 2.1 compliance to SoC devices. The core is capable of responding to cycles for attribute memory,common memory, and I/O modes up to the maximum rate allowed by the PCMCIAstandard. The core is designed to interface to the processor through the CoreFrame?or AHB interface. Direct memory access (DMA) is provided through a FIFO-like interface to an external DMA channel. The CoreFrame bus is a nonpipelined interface incorporating address, data, read strobe, write strobe, and a wait signal. The DMA channel interface is a non-pipelined interface that includes FIFO status, data, and read and write strobes. Interrupt status and masking registers allow polled or interrupt-driven firmware to service interrupt events.
PCMCIA IP- Device Controller
Overview
Key Features
- Supports memory and I/O modes
- Up to 20 MB/s transfer rate in common memory mode
- Up to 17 MB/s transfer rate in PIO mode
- Conforms to PCMCIAcard 2.1 standard
- Data transfer to/from memory via DMA or PIO interfaces
- 256-byte CIS RAM
- 256-byte PIO RAM
- PCMCIA registers accessible in low-power state
- 133 MHz maximum operating frequency in 0.18u
- Supports either CoreFrame or ARM AMBA AHB bus interface
Technical Specifications
Related IPs
- PCMCIA IP Host Controller
- ISA / PC Card / PCMCIA CompactFlash Controller
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- DDR3 Controller IP
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- DDR-I/II/III CONTROLLER IP CORE