The Mentor Graphics?parallel ATA host interface controller provides an efficient and easy-to-use interface to IDE and ATAPI devices. The core implements programmable I/O, multi-word direct memory access (DMA), and Ultra ATA-33, -66, -100, and -133 modes of operation and supports up to two devices. The core interface to the system-on-chip provides PIO access and DMA capability to optimize data transfers to and from the IDE devices. For ease of integration, the core
includes a register set compatible with the Intel chip set, including a descriptor-based, scatter-gather DMAcore. This core is compatible with ATA-4, and with Ultra ATA-33, -66, -100, and -133 extensions. However, single-word DMA is not supported.
Parallel ATA IP Host Controller with Integrated DMA
Overview
Key Features
- Programmable I/O modes: 0, 1, 2, 3, and 4
- Easily configured as primary and secondary IDE controller
- Multi-word DMAmodes: 0, 1, and 2
- Synchronous Ultra ATA-33, -66, -100, and -133 modes: 0, 1, 2, 3, 4, 5, and 6
- Descriptor-based, scatter-gather DMA engine
- Intel register set compatible
- Support for synchronous or asynchronous DMA interface for data transfers
- Supports up to two devices with independent master/slave timing controls
- Supports either CoreFrame or ARM AMBA AHB bus interface
Technical Specifications
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