Multi-channel Limited Baseline HDTV 1080p H.264/AVC Decoder

Overview

Key Features

• Fully compatible with the output of the OL_H264MCE encoder core.
• Up to Profile level 4.1 can be decoded.
• Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive).
• Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps.
• Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in high end FPGAs (Virtex4) . 4 CIF (704x576) at 30 fps in low end FPGAs.
• No CPU required for decoding.
• Very low latency decoding
• Motion vector up to –32.00/+31.75 pixels.
• Support for most of intra4x4 and all intra16x16 modes.
• Multiple slices support for better error resilience.
• Block skipping logic for lower bitrate.
• Deblocking filter for better quality.
• External memory interface tolerant of high latencies and delays, ideal in a SoC system or in a shared bus with a CPU. The memory interface can be clocked at a different frequency from the core for easier integration.
• Supports YUV 4:2:0 video output.
• Min Clock speed = 4 x the raw pixel clock speed.
• Simple, fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.

Deliverables

• Synthesizable VHDL or Verilog RTL.
• Bit accurate C model.
• Complete HDL testbench.
• Complete data sheet.

Technical Specifications