Baseline HDTV 1080p H.264/AVC Encoder Core

Overview

Key Features

• Fully compatible with the ITU-T H.264 baseline specification.
• Proven in FPGA : VGA (640x480) at 30 fps in VirtexII-4 demo board.
• Profile level 4.1, can be decoded by Main Profile decoder.
• Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive).
• Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps.
• Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in high end FPGAs (Virtex4) . 4 CIF (704x576) at 30 fps in low end FPGAs (Spartan3-4, slowest speed grade).
• No CPU required for encoding.
• Variable Bit Rate (VBR) and Constant Bit Rate (CBR).
• Very low latency in VBR (~1.1 ms for VGA @ 30 fps).
• Motion vector up to –16.00/+15.75 pixels (search area is 32x32 pixel wide down to quarter pixel).
• Support for most of intra4x4 and all intra16x16 modes.
• Multiple slices support for better error resilience.
• Block skipping logic for lower bitrate.
• Deblocking filter for better quality.
• External memory interface tolerant of high latencies and delays, ideal in a SoC system or in a shared bus with a CPU. The memory interface can be clocked at a different frequency from the ocre for easier integration.
• Supports YUV 4:2:0 video input.
• Min Clock speed = 4 x the raw pixel clock speed.
• Low gate count : from 129K gates + 100 Kbits of RAM for real time VGA encoding to 178 Kgates + 100 Kbits of RAM for real time 1080p encoding.
• Simple, fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.

Technical Specifications