MIPI RFFE Slave Controller IP Core

Overview

Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial interface which utilizes a bus frequency of up to 26 MHz and timing accurate trigger mechanisms to allow control of timing critical functions. It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers and Antenna Sensors, which are considered RFFE Slaves.

The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.

The RFFE Slave IP Core resides in each RF front end component. At a minimum, Arasan delivers RFFE Slave in RTL form. Optionally, physical designs of the complete RFFE Slave, including the Pad Logic block for CLK and DATA as shown below, can be provided upon request.

Key Features

Compliant with MIPI RFFE Specification 1.10

Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
Optionally delivered as a physical design
Small footprint

Configurable implementation with respect to number and type of registers
Up to 15 Devices can be connected per RFFE bus
Low pin count on RFFE interface (SCLK and SDATA)
Low EMI
Low power consumption
Timing accurate trigger mechanisms, including group triggering
Bitwise low power state support Support Register read register write , register 0 write and Extended Register write and Extended Register read.
RFFE clock speed of 26Mhz
Support for half speed read access for slow RF front end devices

Benefits

Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Premier direct support from Arasan IP core designers

Deliverables

IP Deliverables for RTL Version

Verilog HDL of the IP Core
User guide
Gate count estimates available upon request
Synthesis scripts
Simulation environment including testbench, BFM’s, and exhaustive test suite

Additional Deliverables, for Physical Design (optional)

GDS-II Database
LVS Netlist
Physical Abstract Models (LEF)
Timing Models (LIB)

Technical Specifications

Maturity

Silicon Proven

Availability

Now

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