MIPI D-PHY Universal IP

Overview

The MXL-PHY-MIPI is a high-frequency low-power, low cost, source-synchronous, physical Layer compliant with the MIPI Alliance Standard for D-PHY. Although it is primarily used for connecting cameras and display devices to a cost processor, it can also be used for many other portable applications. It is used in a master-slave configuration. High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

Key Features

Complies with MIPI Standard for D-PHY V1.0
Point-to-point differential interface supporting multiple data lanes and a clock lane
Supports both high speed and low-power modes
Data lanes support both bidirectional and unidirectional modes
Clock lane supports unidirectional communication
80 Mbps to 1Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
Modular design to allow for all possible configurations
Low power dissipation

Benefits

Supports both MIPI CSI-2 and MIPI DSI, as a transmitter and receiver

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

All, Upon request

Maturity

Silicon Proven

Availability

Now

GLOBALFOUNDRIES

Silicon Proven: 130nm

SMIC

Silicon Proven: 110nm G , 130nm LL

TSMC

Pre-Silicon: 28nm HPL , 28nm HPM , 130nm G
Silicon Proven: 40nm LP , 65nm LP , 130nm LP

Tower