MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+

Overview

The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).

The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

  • Consists of 1 Clock lane and up to 4 Data lanes
  • Supports MIPI Standard 1.1 for D-PHY
  • Supports both high speed and low-power modes
  • 80 Mbps to 1.5Gbps data rate in high speed mode
  • 10 Mbps data rate in low-power mode
  • High Speed Serializers included
  • Low power dissipation

Benefits

  • Area and performance optimized for CSI-2 TX applications in production in 28HPC+.

Block Diagram

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ Block Diagram

Video

Mixel Customer Demo - GEO GW5 Warpcam

We demonstrate our customer demo, GEO GW5 Warpcam, featuring Mixel's MIPI D-PHY TX and RX IP.

Applications

  • Mobile
  • Cameras/Sensors
  • IoT
  • VR/AR/MR
  • Consumer electronics
  • Automotive

Deliverables

  • Specifications
  • GDSII
  • LVS netlist
  • LEF file
  • IBIS Model
  • Verilog Model
  • Timing Model
  • Integration Guidelines
  • RTL
  • Documentation
  • One year support

Technical Specifications

Foundry, Node
TSMC, 28HPC+
Maturity
Silicon Proven
Availability
Now
TSMC
Pre-Silicon: 28nm HPCP
×
Semiconductor IP