MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 40LP

Overview

The MXL-DPHY-CSI-2-RX+-T-040LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY.
The IP is configured as a MIPI slave optimized for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

Key Features

Consists of 1 Clock lane and 2 Data lanes
Supports the MIPI Standard 1.1 for D-PHY
Supports both high speed and low-power modes
80 Mbps to 1.5Gbps data rate in high speed mode
20 Mbps data rate in low-power mode
High Speed Deserializers included
Low power dissipation
Loopback testability support

Benefits

Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
Supports full-speed loopback testability with minimal area overhead for high-volume manufacturing tests
Embedded PLL with compact footprint used for generating high-speed clock during test modes and eliminates the need for an external PLL.
One transmitter is used to test multiple receivers to minimize area overhead
Two different loopback modes allow isolation of faults and defects
Analog test bus (ATB) for sensing internal analog voltages and currents

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC 40LP

Maturity

Silicon Proven

Availability

Now

TSMC

Pre-Silicon: 40nm LP
Silicon Proven: 40nm LP

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