The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral
device (camera) and host processor (application engine) for mobile applications.
The MIPI CSI-2 provides the mobile industry a standard, robust, scalable, low-power,
high-speed, cost-effective interface that supports a wide range of imaging solutions for
mobile devices.
MIPI CSI2 Receiver Interface
Overview
Key Features
- Compliance as per MIPI-CSI-2 version3.0.
- Compliance with C-PHY 2.0 for MIPI CSI-2 Version3.0
- Compliance with D-PHY 2.5 for MIPI CSI-2 Version3.0.
- Compatibility with I2C and I3C(SDR,DDR) for CCI interface
- CSI-2 Receiver supports C-PHY 2.0/ D-PHY 2.5/ A-PHY/ M-PHY. Only one PHY layer
- can be configured at a time of transmission.
- Processor Interfaces are AHB Lite/APB/AXI for configuration.
- CSI-2 Receiver Supports Lane merging Function from N-Lanes and consolidate into
- complete packet for LLP.
- In D-PHY, CSI-2 Receiver will detect the de-skew pattern. On communication with low
- transmit frequencies, it will bypass the de-skew mechanism.
- In C-PHY, CSI-2 Receiver supports the sync word detection during payload reception.
- Pixel format supported are: YUV (420/422), RGB (888/666/565/555/444), RAW
- (6/7/8/10/12/14/16/20/24), Generic 8-bit long packet data types, user defined byte based
- data.
- Supports 16 Virtual channels for D-PHY and 32 Virtual channels for C-PHY.
- Supports error detection in data payload, data interleaving, scrambling and descrambling.
- Supports byte to pixel conversion in LLP layer.
Benefits
- Compliance as per MIPI-CSI-2 version3.0.
- Compliance with C-PHY 2.0 for MIPI CSI-2 Version3.0
- Compliance with D-PHY 2.5 for MIPI CSI-2 Version3.0.
- Compatibility with I2C and I3C(SDR,DDR) for CCI interface
- Royalty free
- Good Technical Support
- 100% functional and code Coverage
- C, c++ firmware support
- Integration guide for major Processor interface like ARM, RISC-V, MIPS
Block Diagram
Applications
- Imaging
- Surveillance
- Gaming
- Sensor devices
- Internet of Things (IoT)
- Wearable devices
- Virtual Reality
- Augmented Reality
- Automotive Systems
Deliverables
- Verilog Source Code
- User Guide
- IP Integration Guide
- Run and Synthesis Script
- Encrypted Verification Test-bench Environment,
- Basic Test-suite
Technical Specifications
Maturity
Simulation/FPGA Proven
Availability
immediate
Related IPs
- MIPI CSI-2 Receiver
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- MIPI D-PHY CSI-2 RX (Receiver) IP
- High Performance Second Generation Extended MIPI CSI2 Receiver