IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI CSI-2 IP > MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY

MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY

Overview

The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destination for each data packet (Bayer input of ISP, RGB/YUV input of ISP, Memory). The IP reorders up to 4 x 1Gbps data lanes, separates sensor clock of CSI-2 Core from DPHY byte clock and merges active ones into 32 bits words. The
IP Core is able to store in memory all CSI2 datatype and to process rawbayer, compressed rawbayer, yuv pixel reconstruction for on-the-fly ISP processing. It also performs ECC/CRC check & correction and provides data to SMIA.CSI-2 Receiver IP supports Virtual Channel and Datatype selection. It supports continuous and gated clock configurations

Key Features

  • MIPI Alliance Specification for Camera Serial
  • Configurable DPHY Interface number
  • Configurable Data Lane number (independent for each DPHY I/F)
  • Configurable number of each output type
  • Virtual Channel / Data type de-interleaving
  • Protocol error detection
  • SMIA Protocol handling
  • Byte to pixel conversion
  • Decompression ratios: 6 to 10, 7 to 10, 8 to 10 bpp, 6 to 12, 7 to 12, 8 to 12 bpp, 8 to 14, 10 to 14 bpp
  • On the Fly Processing: Packed outputs
  • Any format packed on 64 bits:Pixel outputs
  • RAW bayer (6, 7, 8, 10, 12, 14 bpp)
  • YUV422 interleaved raster (8, 10 bpp)
  • RGB88
  • Main interfaces: 1 to 4 DPHY interfaces up to 4 data lanes each, compliant with MIPI D-PHY PPI,IRQ lines (level IRQ),Pixel outputs (venv/henv protocol)
  • One pixel per clock cycle: Packed outputs (srdy/drdy protocol)
  • 64 bits wide
  • Flow control (if memory available):ISL outputs (srdy/drdy protocol)
  • 64 bits wide
  • Flow control (if memory available)
  • Mainly intended to store SMIA ISL lines but also usable with only CSI: 32 bits slave interface for register accesses (APB)

Block Diagram

MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY Block Diagram

Deliverables

  • The MIPI CSI-2 Rx Controller interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Technical Specifications

Foundry, Node
Independent, suitable to all 3rd party PHY's
Maturity
In Production
Availability
Immediate
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