MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm

Overview

The MIPI C-PHY/D-PHY combo PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loopback and scan support. It offers a cost-effective and low-power solution.

Key Features

  • Samsung Foundry 4nm low power enhanced (SF4X) CMOS device technology
  • 1.2V±5%, 0.75/0.85V±5% power supply
  • Fully supports MIPI D-PHY v2.0 HS/LP/ULPS Tx/Rx, MIPI C-PHY v1.2 HS/LP/ULPS Tx/Rx (Backward Compatible with previous versions)
  • Supports 80-2500Msps (equivalent to 182.9-5714Mbps) in C-PHY HS mode and 80-4500Mbps in D-PHY HS mode
  • Global operation timing parameters control

Benefits

  • Low power consumption, small area
  • Supports both overdrive (0.85V) and normal (0.75V) power
  • Support for various lane configurations
  • Built-in self-test feature capable of producing and checking PRBS random pattern
  • Highly validated structure in various processes

Block Diagram

MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm Block Diagram

Applications

  • Mobile, Automotive, IoT, DDI, TCON, etc

Deliverables

  • FE-Common: MODEL, TWRAP, TB, LEF, LIBERTY, IPXACT, ATPG, SIPI
  • BE-Common: CIR, GDS, DRC, LVS, DFMC
  • DOC-Common: Datasheet, User Guide, Test Guide, Register Setting Guide, Supplement Guide, PLL Datasheet, PLL Calculator

Technical Specifications

Foundry, Node
Samsung Foundry SF4X
Maturity
Silicon Proven
Availability
Now
Samsung
Silicon Proven: 4nm
×
Semiconductor IP