MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G

Overview

The MXL-CPHY-DPHY-DSI-TX is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display interface DSI. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

Dual mode PHY can support C-PHY and D-PHY
Supports MIPI® Specification for D-PHY Version 1.2
Backward compatible with MIPI® Specification for D-PHY Version 1.1
Supports MIPI® Specification for C-PHY Version 1.0
Four Lane in D-PHY mode
Three Lane in C-PHY mode
Supports both high speed and low-power modes
80 Mbps to 2.5 Gbps data rate in high speed D-PHY mode per lane
80 Msps to 2.5 Gsps (5.7 Gbps) data rate in high speed C-PHY mode per lane
10 Mbps data rate in low-power mode
Low power dissipation
Testability support
Optional resistance termination calibrator

Benefits

Compatible with both C-PHY 1.0 and D-PHY 1.2 specifications for added flexibility

Block Diagram

Applications

Mobile
Displays
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 55G

Maturity

Silicon Proven

Availability

Now

TSMC

Pre-Silicon: 55nm G

Request Info