The Synopsys SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides advanced features such as ADMA3 for the SD 6.0, SDIO 4.10 specifications and Command Queuing Engine (CQE) for the SD 6.0 and eMMC 5.1 specifications. The IP also provides advanced high-performance 32- and 64-bit AXI interface to the system-on-chip (SoC).
The IP architecture leverages power management techniques, making it ideal for low-power applications. The highly configurable and scalable IP is packaged with Synopsys coreConsultant tool and is optimized to reduce gate count and power consumption while ensuring compatibility with previous and future generation SD and eMMC specifications.
A rigorous UVM-based verification methodology is applied to the Synopsys SD/ eMMC Host Controller IP, consisting of directed tests and constrained random verification. The simulation-based verification is further augmented with FPGA hardware verification based on Synopsys’ HAPS®-DX FPGA-based prototyping system. The FPGA development board is tested with all major SD cards, SDIO commands, and eMMC devices. The IP is in volume production and has been successfully implemented in a wide range of applications.
Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
Overview
Key Features
- Compliant with SD HCI specification
- CQE capable of reordering task execution based on priority
- Data prefetching for back to back tasks—further improves random IOPS
- Low-power features with power gating and multi-power rails
- Independent clock domains help in shutting down intelligently to save power
- Support for in-line encryption
- UVM-based verification approach with single Test Environment for SD 6.0, eMMC 5.x, SDIO 4.10 specifications
- Includes high-performance 32- and 64-bit AXI bus interface
- Support for advanced DMA modes to improve data transfer between system memory and SD card
- Data buffering with configurable FIFO depth and automatic packing/unpacking of data to fit FIFO width
- Combined and separate interrupt outputs with support for interrupt enabling and masking
- Scatter—gather DMA
- Configurable block size (1 to 65,535 Bytes)
Benefits
- Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
- Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
- Low power features with power gating and multi-power rails
- Supports host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
- Includes high-performance 32- and 64-bit AXI bus interface
- Supports multiple options for software-based, software-assisted and hardware-driven tuning
Applications
- Mobile
- Consumer
- Internet-of-Things (IoT)
- Automotive
Deliverables
- Databook
- Application notes
- CoreTools packaged customer configurable Verilog RTL source code
- Synthesis scripts for Synopsys Design Compiler
- Verification testbench, test cases and test configurations
Technical Specifications
Maturity
Available on request
Availability
Available
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