Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks

Overview

Key Features

• 100MHz up to 1.1GHz input/output frequency range
• Static phase-phase variation better than +-1.8% of output period
• Optional 8-phase output mode for power savings
• Small footprint (0.03mm^2)
• Low power (<5mW @ 800MHz)
• Low jitter: Long Term Jitter < 3% of output period (p-p, 6-sigma)
• Low jitter: Period Jitter < 1.5% of output period (p-p, 6-sigma)
• Built-in supply decoupling
• Simple digital control interface

Benefits

• Accurate generation of accurate 16-phase clocks can replace a DLL in many calibration systems
• High bandwidth PLL quickly adjusts to track input phase variations while filtering high frequency input noise to minimize phase-phase disturbances
• No external components required
• No additional supply decoupling required
• Loop automatically adjusts for any input frequency, so no complicated programming is required

Deliverables

• GDSII
• CDL Netlist (MG Calibre Compatible)
• Functional Verilog Model
• Liberty timing models (.lib)
• LEF
• Application Note

Technical Specifications