LDPC codec for NAND FLASH error correction
Overview
The LDPC IP is aLow-densityparity-check code encoder and decoder designed for 3D NAND Flash error correction to address the reliability challenges. 1kB, 2kB and 4kB code information lengths are supported.
Key Features
- Strong error correction performance
- Supporting wide range of data-rates from 0.89 to 0.95
- No error floor @UBER=10E-15
- High throughput (up to 2.8GBps) with low complexity hardware
- Hard decision and multi-bits soft decoding support
- Error bits number output when decodable
- Original frame output when un-decodable
- Early termination technique
Deliverables
- Source Code for Matlab simulation and matrix information
- Source Code for fast simulation on Nvidia GPU
- Verilog HDL Source Code for En/Decoder IP
- IP Verification Environment
- FPGA Verification Environment Reference Design
- IP User Guide
- IP Test Documantation
- Integration support including consulting
Technical Specifications
Related IPs
- Flash Memory LDPC Error Correction
- NAND Flash controller supporting MLC Flash with multi-bit correction BCH ECC code
- Flash Memory Controller IP, Support page sizes of 512, 2K, 4K, 8K and 16K bytes NAND Flash memory, 74bit ECC correction (512 or 1K bytes sectors), Soft IP
- LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core