Flash Memory LDPC Error Correction
Overview
The Xilinx® LogiCORE™ IP Flash Memory low-density parity-check (LDPC) Error Correction core is a major component for improving flash reliability. It implements the encoding and decoding functions for cloud and data center storage applications. The core utilizes advanced code construction methodology and proprietary optimization technique to achieve best code performance and low error floor. It is also designed with high resource efficiency and low latency and can be targeted to Virtex®-7, Kintex®-7, Virtex UltraScale™, and Kintex UltraScale devices
Key Features
- Best-in-class code performance near Shannon limit
- Achieved low error floor under 1e-15 with proprietary optimization method
- Support for code rate change on-the fly
- Support for both hard decision and soft decision decoding
- High throughput and low latency performance
- FPGA optimized for minimal area and power
- Provides decoder status and statistics interfaces
Technical Specifications
Related IPs
- LDPC codec for NAND FLASH error correction
- LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
- Flash Memory LDPC
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- NAND Flash controller supporting MLC Flash with multi-bit correction BCH ECC code
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core