IP Compiler for PCI Express x4 (Soft IP)

Overview

These popular PCIe MegaCore® functions (x1, x4, or x8 lane configurations) support all memory, I/O, configuration, and message transactions. The MegaCore functions have an optimized application interface to achieve maximum effective throughput. The MegaCore functions are also flexible and configurable, allowing customization for your specific needs. For example, the MegaCore functions support a configurable payload and a configurable retry buffer, and provide optional support for high-reliability features, such as ECRC and AER.

Altera has performed significant hardware testing of the PCIe x1, x4, and x8 endpoints to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCIe switch chips, and embedded microprocessors. Additionally, the soft IP MegaCore functions were tested at the PCI-SIG compliance workshops and passed with high quality results, including a 100 percent passing rate for the PCI-SIG® gold tests.

Key Features

  • Feature rich
  • Intellectual property (IP) compliant with PCI Express® (PCIe®) base specifications 1.0a and 1.1, with Gen1 x1, x4, and x8 lane support for endpoint applications
  • Optional end-to-end cyclic redundancy check (ECRC) and advanced error reporting (AER) for high-reliability applications
  • Ease of use
  • Avalon®-Streaming (Avalon-ST) and Avalon Memory-Mapped (Avalon-MM) interfaces
  • Easy adoption with OpenCore Plus hardware evaluation
  • Easy configuration using simple GUI
  • Multiple design examples to jump start your designs
  • Robust solution
  • Industry-compliant IP
  • Support for soft IP on Altera® development kits:
  • Arria® II GX FPGA Development Kit
  • Arria II GX FPGA Development Kit, 6G Edition
  • Cyclone® IV GX FPGA Development Kit
  • Stratix® IV GX FPGA Development Kit
  • Stratix IV GX FPGA Development Kit, 530 Edition

Benefits

  • SOPC Builder Ready: Yes
  • Qsys Compliant: No

Technical Specifications

×
Semiconductor IP