Interleaver / De-interleaver
Overview
The Interleaver/De-interleaver LogiCORE™ module is a high-speed, compact design that is fully synchronous, using a single clock. It's parameterizable features support both the Forney Convolutional architecture and the Rectangular Block architecture. The number of branches and branch lengths are parameterizable. The core supports a symbol size from 1 to 256 bits.
Key Features
- High-speed compact symbol interleaver/de-interleaver with AXI4-Stream interfaces
- Supports many popular standards such as DVB and CDMA2000
- Supports both the Forney Convolutional and the Rectangular Block architectures
- Supports a symbol size from 1 to 256 bits
- Generate example VHDL testbench
- Internal or external symbol RAM
- Convolutional interleaver supports multiple configurations with on-the-fly swapping
- For use with Vivado® IP Catalog and Xilinx System Generator for DSP™
Technical Specifications
Related IPs
- Interleaver / De-interleaver
- Interleaver/De-Interleaver
- Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
- Radiation-Hardened eFPGA
- UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N5 X8, North/South (vertical) poly orientation