IEEE802.15.3c irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder.
The implementation provides: (a) High throughput. Datarates
higher than the raw data rates of single carrier (SC) PHY
mode, and high speed interface (HSI) PHY mode; (b) Low-power
consumption and logic controlled gated clocks; (c) High silicon
utilization and reduced gate count; and (d) Low error rates with
both fine and coarse signal quantization.
Please contact Continuous-bits for the other variant availability (LDPC(1440,1344) ).
IEEE 802.15.3c Irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder
Overview
Key Features
- Belief-propagation iterative decoding
- Pipeline design, 4 clocks perdecoding iteration
- Single clock synchronous design; registered inputs and outputs;
- Single-port memories only
- Portable to all ASIC technologies
- On-the-fly configuration, with each codeword, of code rate and maximal number of iterations to simplify the use with unequal error protection (UEP) MSC.
- Continuous monitoring of convergence enables early stop of iterations when a codeword is found
- Low power design. Dedicated logic gates the clock to parts of decoder when no data is available for decoding
Technical Specifications
Short description
IEEE 802.15.3c Irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder
Vendor
Vendor Name
Foundry, Node
Portable to all ASIC technologies