IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput. The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.
IEEE 802.3bj Reed-Solomon Encoder and Decoder
Overview
Key Features
- Compliant with IEEE 802.3bj, Clause 91
- Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
- Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols
Benefits
- High-throughput, low-latency core
- Support for single channel mode (up to 100 Gbit/s)
- Support for bypass mode with low laten
- Symbol error measurement per lane
- Detection of un-correctable code words
- Block-to-block on-the-fly switching between KP4/KR4 codes
- Easy-to-use handshaking interfaces.
- No internal RAM required
- Available for ASIC and FPGAs (AMD Xilinx, Intel)
- Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
Block Diagram
Applications
- KR4 single channel
- KP4/200 g single channel
- KP4/KR4 single channel
- KP4/KR4 multi channel
- KP4/KR4/RS272 single channel
- KP4/KR4/RS272 multi channel
Deliverables
- VHDL or Verilog source code or synthesized netlist
- HDL simulation models e.g. for Aldec’s Riviera-PRO
- VHDL or SystemC testbench
- bit-accurate Matlab, C or C++ simulation model
- comprehensive documentation
Technical Specifications
Availability
Now