IBM 65nm LPE Process 10Bit 2-Channel 40MHz ADC
Overview
The VeriSilicon I65LPEV25_ADC_06 IP is a 2.5V 10Bit 40MHz pipeline analog to digital converter capable of running at up to 80MHz conversion rate in one channel mode or 40MHz in I&Q channel mode，with 2Vp-p input range. The ADC cell implements a pipeline (1.5B per stage) sampling architecture which includes SHA, 8 scaled stages and 2bit flash stage. It has a fully differential structure and the power consumption is dynamically scalable with operating frequency.
Key Features
- 10bit up to 80MSPS conversion rate in single channel mode
- Up to 40MSPS conversion rate in I&Q channel mode
- 2.0Vp-p differential input swing
- Supply voltage: 2.5V analog power, 1.2 V digital power
- Excellent dynamic performance: --56dB SNR at Fin=5MHz /--62dB THD at Fin=5MHz /--65dB SFDR at Fin=5MHz
- Fully differential structure:
- Power consumption :---I&Q channel sampling at 40MHz : 47mA
- Operating junction temperature: -40°C ~ +60°C ~ +120°C
Technical Specifications
Foundry, Node
IBM 65nm