IBM 65nm 12-Bit 8-Input 1M/200k SAR ADC

Overview

This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core internal SAR ADC, 8-1 MUX and touch screen drivers. The internal SAR ADC includes sample/hold circuits, a capacitive DAC, a comparator and logic control circuits.

External reference or internal reference is needed. In addition, the reference voltage input will be adjusted to allow encoding smaller analog voltage spanning to the full 12 bits of resolution.

The ADC has dual speed modes – 1M or 200K - working in 200K mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power.

The ADC is especially suitable to act as Touch Screen Controller, demanding less off-chip components to complete the design.

Battery voltage detection could be easily accomplished by the SAR ADC. It has an in-chip resistor divider. Keypad interrupt signal generator is integrated in this SAR ADC too.

The converter has flexible control logic, and could be easily embedded in a complex system.

It is also suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.

Key Features

  • Process: IBM 65nm SF
  • Resolution: 12-bit resolution
  • DNL: +/-2 LSB, INL: +/-4 LSB
  • Dual Data Rates: 1MSPS/200KSPS
  • Analog Input Range: VREF to AGND, could be rail-to-rail
  • Analog supply: 2.25 - 2.75V; Digital supply: 0.9 – 1.1V
  • 8 Single-Ended Analog Inputs
  • 4-wire Touch Screen Interface
  • Touch Pressure Measurement
  • Direct Battery Measurement
  • Keypad Interrupt Generator
  • Auto Power Down
  • Low Power Consumption: 3850μW(@1MSPS) / 2320μW(@200KSPS), < 10μA (Auto power down mode)
  • Flexible control logic: to be easily embedded in a system, or operates “stand alone"

Technical Specifications

Foundry, Node
IBM 65nm
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Semiconductor IP