High Performance SHA-1 Hash Core for Xilinx FPGA

Key Features

• Implements the SHA-1 secure hash algorithm to NIST FIPS Publication 180-1
• Fast operation - each 512-bit block requires 81 master clock cycles (1 clock per algorithm step + 1 clock load)
• Performs automatic message length calculation and padding insertion
• Optional user initialisation of IVs for efficient HMAC support
• Simple external interface
• Highly optimised for use in Xilinx FPGA

Benefits

• Xilinx Spartan3 –4
• typical core gate count: 677 slices/0 blockrams
• max master clock: 87 MHz
• max data rate: 543Mbps
• Xilinx Virtex2 –6
• typical core gate count: 573 slices/0 blockrams
• max master clock: 140 MHz
• max data rate: 874Mbps

Deliverables

• Target specific netlist or fully synthesisable RTL VHDL/Verilog
• VHDL/Verilog simulation model and testbench with FIPS test vectors
• Comprehensive user documentation

Technical Specifications