The IPM Host NVMe is a verilog IP to be integrated in a FPGA. It fully manages the NVMe protocol on the host side without requiring any CPU. It can be used with any NVMe SSD available on the market, or with a custom design based on the NVMe Device IP from IP-Maker. The Host NVMe is well suited for embedded applications requiring a high throughput storage such as recorder and video applications. 1+ million IOPS performance requires the use of an expensive CPU, which is not feasible in an embedded system due to cost, space and power limitation.
NVM Express IP Core
Overview
Key Features
- Ultra low latency
- Very high throughput
- Low power architecture
- Low gate count
- No need of CPU
- Easy integration
- Ease of use
Benefits
- NVM Express Compliant
- Automatic PCIe/NVMe init
- Up to PCIe Gen 3x8
- IO read/write and shutdown commands
- FIFO or AXI4 or Avalon interface
- 128 or 256 bits data path
Block Diagram
Video
This is the NVM Express demo from IP-Maker demonstrated at Flash Memory Summit 2012, Santa Clara, CA. The NVMe IP is integrated in a FPGA-based board including all the mandatory features of the NVM Express specification 1.0d. NVMe protocol is observed wit
This is the NVM Express demo from IP-Maker demonstrated at Flash Memory Summit 2022, Santa Clara, CA. The NVMe IP is integrated in a FPGA-based board including all the mandatory features of the NVM Express specification 2.0. NVMe protocol is observed with a protocol analyzer from Teledyne Lecroy.
Applications
- PCIe SSD
Deliverables
- Verilog RTL source code
- Low level firmware
- Synthesis scripts
- Technical documentation
- Technical support
Technical Specifications
Related IPs
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- BCH Encoder/Decoder IP Core
- Universal NVM Express Controller (UNEX)
- DDR-I/II/III CONTROLLER IP CORE
- Vector Graphics IP core supporting OpenVG1.1 subset
- 10G/25GBASE-R PCS+KR4 FEC IP Core