High-performance Processor for Real-time and Linux Applications

Overview

Key Features

• Optimized pipeline for best performance with over 1 GHz
• Dynamic branch prediction accelerates loop execution
• Unified Local Memory (ULM) for simultaneous accesses
• 64-bit AXI bus for high bandwidth and low latency
• MMU and MPU for Linux and RTOS
• Support for FPU coprocessor and L2 cache

Benefits

• Performance
  • Highly compact program size through AndeStar™ V3 ISA
  • Optional saturation instructions for efficient voice applications
  • Single-cycle latency for most of 32-bit operations
  • Extensive branch predictions to speed up branch control
  • Efficient atomic access synchronization without locking system bus
  • Low latency vectored interrupt improving real-time performance
  • Single-cycle local memory interface with adjustable wait cycles
  • Optional 2D Local Memory DMA for efficient data transfers
  • Optional 64-bit datapath between bus and caches with power reduction architecture
  • Optional HW page table walker for MMU
  • Processor state bus to simplify SoC design and debugging
• Flexibility
  • Easy arrangement of preemptive interrupts
  • Memory-mapped IO space
  • All-C Embedded Programming
  • Stack protection hardware to help determining stack size needed, and detect runtime overflow error
  • PC-relative jumps for position independent code
  • JTAG-based debug support
  • Performance monitors
  • Support for bi-endian data accesses
  • Support boot-up from AXI if both AHB and AXI exists
  • Optional unified local memory interface for flexible code and data location
• Power Management
  • Highly clock gating and logic gating
  • Standby instructions to help power management
  • N:1 core vs bus clock ratios
  • PowerBrake technology to reduce peak power consumption

Block Diagram

Applications

• Networking device
• WiFi device
• GPON
• Surveillance system
• ADAS
• Storage device
• Digital TV/Set top box
• Media center

Technical Specifications