High performance, flexible, 32 bit Energy Efficient Embedded Microcontroller

Overview

The APS5 is a fully 32 bit general purpose CPU, designed to provide meet and exceed the needs of the most demanding embedded systems. It provides higher throughput integer processing than the APS3 with increased configurability, notably with a tightly integrated co-processor interface.

Detailed information can be obtained once a non-disclosue aggrement has been signed (NDA).

The entire GNU GCC toolsuite has been ported to this architecture.

Key Features

High Throughput RISC Core
2.24 DMIPS/MHz
5-stage pipeline
High Clock Frequency (> 400MHz in 90nm)
Optional Instruction Cache
Optional Data Cache
Optional Memory Management Unit
Optional co-processors (user & Cortus designed)
Integer Divider
Integer Multiply
Up to 250 Low Latency Vectored Interrupts
Dual & Multi-core Capable

Benefits

High performance embedded CPU
Compact silicon footprint, less silicon area
High maximum clock frequency
Good Code Density, less Flash memory required
Dual and Multi-Core, more performance without exploding consumption
Co-processor interface, add algorithmic functionality in hardware, save time and power.
Optional instruction and data caches
RTOS support: FreeRTOS, uCLinux, uC/OS II, uC/OSIII, TargetOS
Full Development Environment
Optional Ethernet 10/100 MAC and USB2.0 Peripheral
Optional JTAG-Ethernet Debug Solution

Block Diagram

Applications

Powerline communications
Vision systems (e.g. surveillance, automotive)
High performance embedded systems
Symmetric multi-processing systems

Deliverables

Full Verilog Source Code
Full Toolchain
Graphical Development Environment
Debugger
Standard Peripherals
Full Documentation
Complete Integration Guide
Supplied as Part of a Design Services Contract

Technical Specifications

Foundry, Node

All

Maturity

In production

Availability

Now

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