64-bit in-order RISC-V Customisable IP Core

Overview

Key Features

• 64-bit Core
• (RISCV64GCV)
• 2-wide In-Order
• Multiprocessor Ready
• (AXI/CHI)
• Direct hardware support for unaligned accesses
• MMU Linux Ready
• Available extensions
  • Bit Manipulation
  • CMO’s
  • Half/bf16/Single/Double
  • Zifencei
  • Crypto
  • Open Vector interface
  • Vector Unit
• Customisable options
  • Vector spec 1.0 (vector ready)
  • Branch Predictor
  • I$ from 8KB to 32KB
  • D$ from 8KB to 32KB
  • Gazzillion Misses™

Block Diagram

Applications

• Machine Learning
  • The Avispado core, with its small area and power, is ideal for energy-conscious SOCs targeting Machine Learning.
  • If your next SoC is targeting the Machine Learning market, then Avispado’s small footprint combined with its ability to talk to a RISC-V Vector Unit (1.0) is the perfect fit for your target.
  • Combined with our Gazzillion technology, Avispado can deal with very high sparsity in tensor weights, resulting in excellent Energy per operation.
• Recommendation Systems
  • The Gazzillion technology is specifically designed for Recommendation Systems, a key part of DataCenter Machine Learning.
  • By supporting hundreds of misses per Avispado, you can build an SoC that smoothly delivers highly sparse data to compute engines without a large silicon investment.

Technical Specifications