64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems

Overview

Key Features

• Configurable instruction set architecture:
  • 64-bit RISC-V with 32 integer registers (I extension)
  • Integer multiplication and division (M extension)
  • Atomic operation support (A extension)
  • Compressed mode for better code density (C extension)
  • IEEE 754-2008 compliant single precision floating point (F extension)
  • IEEE 754-2008 compliant double precision floating point (D extension)
  • Bit manipulation instructions support (B extension)
  • Scalar cryptography instructions support (K extension)
  • Digital signal processing instructions support (P extension)
• Dual instruction issue
• Up to 4 cores in complex
• Machine, Supervisor and User modes
• 8 stage in-order pipeline
• Advanced branch predictor: BTB, BHT, RAS
• Sv39 Virtual Memory support
• 4 to 32 KiB, 2 to 8-way L1 I-cache
• 4 to 32 KiB, 2 to 8-way L1 D-cache
• Integrated 128 KiB to 2 MiB L2 Cache
• L2 stride prefetcher
• Interrupts
  • Platform Level Interrupt Controller (PLIC)
  • Multi-Core Local Interruptor (CLINT): timer + software interrupts
  • Local interrupt support to provide fast handling
  • Core Local Interrupt Controller (CLIC)
  • Non-Maskable Interrupts (NMIs)
• ECC memory protection (SEC-DED)
• Physical memory protection
• Integrated debug controller including HW breakpoints
• System bus access
• Compact JTAG support
• Power management support
• AXI system interface
• AXI peripheral interface
• AXI front-port interface for accelerator coherent access
• Performance
  • 2.93 DMIPS/MHz
  • 5.73 CoreMark/MHz
• Frequency
  • 1 GHz (TSMC, 40nm G, SSG corner)
  • 1.2 GHz (TSMC, 28nm HPC+, SSG corner)

Benefits

• SMP support and accelerator coherency
  • BI-652 has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Additional coherency controller provides coherent access for accelerators via AXI front port to cached memory ranges simplifies software development and improves performance
• Development Tools
  • Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start
• 3rd Party Development Tools
  • IAR Embedded Workbench®
  • SEGGER Embedded Studio for RISC-V
  • TRACE32® debugger for RISC-V
• Compatible Debug Probes
  • BI-652 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
    • Digilent HS2
    • Digilent HS3
    • Olimex ARM-USB-TINY
    • Olimex ARM-USB-TINY-H
    • Olimex ARM-USB-OCD
    • Olimex ARM-USB-OCD-H
    • SEGGER J-Link
    • TRACE32® debugger for RISC-V

Block Diagram

Technical Specifications