HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5)

Overview

Key Features

• Low latency, small area, low power
• Compatible with JEDEC standard HBM2/HBM2E SDRAMs
• Data rates up to 2400 Mbps for HBM2 and 3600 Mbps for HBM2E
• 4H and 8H HBM2/HBM2E SDRAM stacks supported
• Support for fast switching between 4 frequencies
• Product subcomponents designed to precisely control timing critical delay and skews
• Controller DFI-compatible interface (DFI v4.0 Addendum 2)
• PHY supports 1:1 and 1:2 modes (PHY:SDRAM clock ratios)
• Includes 1 phase-locked loop (PLL) per PHY and digital delay lines necessary to meet timing specifications
• PLL allows bypass mode that enables PHY to be run at low speeds
• Separate transmit DQ and transmit DQS as well as transmit Row/Col and transmit CK delay lines
• Allows de-skew of transmit DQS/CK vs. transmit DQ/Row-Col, respectively
• Includes separate receive DQS delay lines for both rising and falling edge of DQS
• Supports 8-channel HBM2/HBM2E DRAM systems
• Supports pseudo-channels as defined in the JEDEC HBM2/HBM2E standard
• Boot time impedance calibration
• Programmable I/O drive strength matching the HBM SDRAM
• Delay line VT compensation
• Time axis data eye training
• Internal finite state machine (FSM) allows automated training to optimum setting
• Alternative software hooks included to allow external software to program optimum setting
• PHY VREF can either be supplied externally through a bump or use an internal VREF generator that can provide a programmable VREF for use internal to the PHY
• Internal VREF generator is programmable from 0 to VDDQ
• Physical implementation of the top-level HBM PHY hard macro is designed to be compatible with a face centered rectangular (FCR) micro bump pattern similar to the JEDEC standard HBM2 SDRAM micro bump pattern with a minimum of 55um center-to- center spacing
• Permits shortest 2.5D routes between PHY and HBM2/HBM2E SDRAMs for highest signal integrity
• Enhanced power savings support that includes:
• Per-channel DFI_LP
• PHY leakage mode with fast exit (<5us)
• PHY controls to support DRAM retention mode
• ARM® AMBA ® APB interface for configuration register access
• Test data register (TDR) interface for configuration register access
• Multiple test modes
• Delay line oscillator test mode
• Mux-scan ATPG
• At-speed loopback testing on both the address and data channels
• Pre-hardened HBM PHYs are available in select process technologies
• Services available for custom PHY hardening requirements
• 2.5D Interposer reference designs available

Benefits

• Supports 2.5D-based JEDEC standard HBM2/HBM2E SDRAMs with data rates up to 3600 Mbps
• 8 independent memory channels (e.g., 1024 bits)
• Pseudo-channel operation supported to enable up to 16 channels with 1024 bit PHY
• Supports up to 4 trained frequencies with <5us switching time
• DFI 4.0-compatible controller interface
• PHY independent training capability
• Comprehensive set of design-for-test (DFT) features

Applications

• High-performance computing
• Graphics
• Networking
• Artificial intelligence
• Machine learning

Deliverables

• Executable .run installation file, including GDSII, LEF Files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample verification environment, PHY data book, physical implementation guide, application notes, verification guide, installation guide, implementation checklist
• The PHY Utility Block includes Verilog code, synthesis/STA constraints and scripts, sample verification environment, data book

Technical Specifications