GSMC0.18um PCI I/O Cells DUP Library
Overview
VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P5M Salicide 1.8V/3.3V process. This library supports Device Under Pad (DUP). This library can take 5V tolerance. This library is fully compliant with the revision 2.2 of PCI local bus specification.
Key Features
- GSMC 0.18um Logic 1P5M Salicide 1.8V/3.3V process
- 1.8V core and 3.3V External interface
- Low area and low cost design using DUP technique
- Meets the revision 2.2 of PCI local bus specification
- Suitable for five metal layers of physical design
- Easy interface with VeriSilicon GSMC 0.18um process standard I/O libraries
Deliverables
- Databook in electronic form
- Verilog models, Synopsys synthesis models and Cadence TLF models
- Candence Silicon Ensenble Abstracts (LEF), Synopsys Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
GSMC0.18um
Availability
Now