The Fast Ethernet Media Access Controller (FEMAC) with AHB or AXI Interface core incorporates the essential protocol requirements for operation of 10/100 Mbps Ethernet/IEEE 802.3-2008 compliant node, and provides interface between the AHB or AXI Interface and the Media Independent Interface (MII) for the Ethernet operation. Optionally the core supports RMII (Reduced MII Interface) and SMII (Serial MII Interface) for reducing the pin count to interface with external PHY device.
The FEMAC Core can operate at 10 Mbps or 100 Mbps (Fast Ethernet) Speed with hardware assisted support for IEEE-1588 protocol. On the System side the FEMAC Core implements 32-bit or 64-bit AHB/AXI Master Interface logic and 32-bit AHB/AXI Target Interface logic to interface with AHB/AXI Bus and a powerful 32-bit or 64-bit Scatter-Gather DMA to transfer packets between HOST Memory and Internal FIFO’s. The FEMAC Core supports configurable FIFO’s on both transmit and receive side to handle the Application’s latency during the frame transmission and reception.
The FEMAC Core supports Half-Duplex mode as well as Full-Duplex mode of operation for 10/100 Mbps. When operating in the half-duplex mode, the FEMAC Core is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard) and ANSI/IEEE 802.3. When operating in the full-duplex mode, the FEMAC core is compliant to the IEEE 802.3 standards’ for full-duplex operations.
The 10/100 Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and has passed inter-operability testing at UNH-IOL. The 10/100 Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and an optional processor interface; it also supports Reduced MII (RMII) and Serial MII (SMII).
The 10/100 Ethernet MAC IP is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers, and Ethernet adapter cards.
