Fast Ethernet 802.3 Media Access Controller (MAC)

Overview

The Arasan 10/100 Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The 10/100 Ethernet - AHB IP core provides a 10/100 Mbps Media Independent Interface (MII), an optional RMII interface, and an AHB master/slave interface. The IP core is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers,and Ethernet adapter cards

Key Features

General Functions:

Full-duplex and half-duplex mode of operation
IEEE 802.3-2008 compliant MII interface
Optional support for RMII interface to reduce pin count
Independent 32-bit scatter-gather DMA with big/little endian operation
Optional VLAN Q-Tag frame support
CSMA/CD Protocol for half-duplex mode
PAUSE frame based flow control in fullduplex mode
MDIO/MDC management interface
802.3 compliant MIB, SNMP, RMON management support
Configurable transmit and receive FIFOs
Supports Jumbo frames
Support magic packet and Wake-Up frames
AHB master/slave interface

Transmit Functions:

Variable length Inter Frame Gap (IFG) on back to back frame transmission
Variable length (3, 5, 7 bytes) preamble generation
Automatic generation of FCS and PAD
Automatic retransmission on collisions in Half-duplex
Option to disable PAD or CRC32

Receive Functions:

Inter Frame Gap checking
Preamble detection and stripping
Flexible address filtering modes and inverse address filtering
64-bit hash table to filter multicast addresses
Promiscuous mode of operation
Reception of broadcast frames
Automatic checking the FCS field, runt frames, and data field length
Detection of MaxFrameLen frames, receive errors
32-bit status information on each receive frame

Flow Control Functions:

Software controlled PAUSE control frame generation including multicast and unicast address.
Automatic detection and checking of PAUSE frames
Option to block PAUSE frames

Benefits

Fully compliant core with proven silicon
Premier direct support from Arasan IP core designers
Easy-to-use industry standard test environment
Unencrypted source code allows easy implementation
Customer training available
Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass

Deliverables

RMM Compliant Synthesizable RTL design in Verilog
Easy-to-use test environment
Synthesis scripts
Technical documents

Technical Specifications

Maturity

Silicon Proven

Availability

Now

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