Ethernet MAC 40G/100G

Overview

Comcores Ethernet MAC 40G/100G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited for use in networking equipment such as switches and routers. Comcores Ethernet MAC is silicon-proven and designed for easy integration into ASICs and FPGAs.

The Client-side interface is a 128-bit AXI-S and comes with 128-bit XLGMII or CGMII interfaces on the PHY side. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC IP is prepared for easy integration with Comcores Ethernet PCS 40G/100G IP solution.

Key Features

Delivers Performance

Designed to IEEE 802.3-2018 specification
Low latency and compact implementation
Full duplex Ethernet interfaces

Highly Configurable

128-bits AXI-Stream interface
Comes with XLGMII or CGMII as default PHY interface
40G/100G data rates with cut-through operation mode, store and forward is optional
Can be delivered with IEEE 1588 and/or 40G/100G PCS

Feature Rich

Deficit Idle Count for maximum data throughput supported
FCS generation supported
Optional statistics gathering
Jumbo frames support
Easy integration with standard AXI4-Lite control interface or APB
Promiscuous and non-promiscuous mode
Optional MDIO interface

Silicon Agnostic

Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

Solid documentation, including User Manual and Release Note
Simulation Environment, including Simple Testbed, Test case, Test Script
Programming Register Specification
Timing Constraints in Synopsys SDC format
Access to support system and direct support from Comcores Engineers
Synopsys SGDC Files
Synopsys Lint, CDC and Waivers

Technical Specifications

Maturity

Mature

Availability

Available

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