Ethernet MAC 10M/100M/1G/2.5G

Overview

Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side.

The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.

Key Features

Delivers Performance
- Designed to IEEE 802.3-2018 specification
- Low latency and compact implementation
- Full duplex Ethernet interfaces
Feature Rich
- FCS generation and jumbo frames supported
- Optional comprehensive statistics gathering
- Independent TX and RX Maximum Transmission Unit (MTU) frame length
- Promiscuous and non-promiscuous mode
- Optional MDIO interface
Highly Configurable
- 8-bits AXI-Stream interface
- Cut-through operation mode, Store and Forward is optional
- Optional IEEE 1588 Support
- Comes with GMII as default PHY interface – MII and RGMII can be optionally selected
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format.
The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case and Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional).
- Synopsys Lint, CDC and Waivers (optional).

Technical Specifications

Maturity

Mature

Availability

Avaliable

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