DO-254 Soft Error Mitigation

Overview

The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification. The core utilizes device primitives such as Virtex™-7 ICAP and ECC blocks to clock and observe the readback CRC circuit as part of the SEU detection function. For SEU correction, the IP core performs the necessary operations to locate and correct SEU errors using the Virtex™-6 built-in ECC facility. For SEU classification, the IP core uses Xilinx Essential Bits technology to further increase system reliability.

The SEM IP core also performs emulation of SEUs within 7-Series, Virtex™-6 and Spartan®-6 devices by injecting errors into the configuration memory. The error injection feature provides a means to evaluate and test the readback CRC circuit and the error correction capabilities of the IP core which is impossible with real SEUs.

Key Features

Automatically detects, corrects, and classifies SEU errors
Supports error injection so all aspects of a system can be evaluated
Supports up to 100 MHz clock.
Functions as "Intelligent Sensor" that connects to the system
Includes simple UART interface to connect to either a terminal or embedded processor
Supports VHDL and Verilog

Benefits

Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.

Deliverables

Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.

Technical Specifications

Availability

AVAILABLE

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