DDRI/II/III SSTL/HSTL combo interface with RTT (square) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF
Overview
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 3.1 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
Technical Specifications
Foundry, Node
TSMC 55nm
Maturity
Pre Silicon
Availability
Available
TSMC
Pre-Silicon:
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
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