DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
Overview
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
Technical Specifications
Foundry, Node
UMC 90nm
Maturity
Silicon proven, Formal release
UMC
Pre-Silicon:
90nm
G
,
90nm
LL
,
90nm
SP
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