DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Overview
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
Technical Specifications
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm
Related IPs
- Gen 2 DDR multiPHY IP
- DDR multiPHY IP
- General Purpose Input / Output Controller (GPIO)
- PCI-X Arbiter Supporting 66 / 100 / 133MHz
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- Horizontal Down-scaler (Customized to two input resolutions and two output resolutions)**