DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Overview
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
Technical Specifications
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm