CMMB LDPC decoder

Overview

Key Features

• 1/2 and 3/4 code rates supported
• One clock synchronous design; registered inputs and outputs; global asynchronous reset
• Portable to all FPGA and ASIC technology
• FPGA proven, maximal clock frequency on Altera Stratix and Xilinx Virtex is over 100 MHz
• Internal double buffer for continuous decoding with maximal efficiency
• On-the-fly configuration of the maximal number of iterations
• Continuous monitoring of convergence enables early stops the iterations when a codeword is found
• Available as VHDL and Verilog codes
• Low power design.

Technical Specifications