Clock and Data Recovery of HDB3/B3ZS coded signals

Overview

Key Features

• Performs receive clock and data recovery on HDB3/B3ZS coded data.
• Programmable jitter attenuator.
• Loss of signal detection.
• Frequency aided acquisition using external reference clock.
• Fast acquisition time.
• Narrow bandwidth digital phase locked Loop.
• NCO used for an all-digital implementation.

Block Diagram

Deliverables

• Synthesizable VHDL or Verilog source code.
• VHDL or Verilog test bench with example configuration files.
• Synthesis scripts.
• Users manual.
• Free 3 months technical support.

Technical Specifications