This is fully configurable Elastic Biffer with configurable Depth, Configurable width. Internal Storage Memory is implemented by Registers.
It has internal CDC methodology which make it possible to transfer data between two clocks even they are of the same freq or there is very small difference between them.
This is capable to transferring data even when internal or exteral clock swings and overlaps each other
Overview
Key Features
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Configurable Data Release Duration.
Benefits
- 1. Fully stable operation.
- 2. Non-2**n depth supported.
- 3. Dip-In and Data Available support.
Applications
- Internal IP Component Block
- can be used inside any IP/SOC.
Deliverables
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
Technical Specifications
Maturity
Final, Stable, High
Availability
Avaliable
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