AXI2APB bridge

Overview

Key Features

• AMBA AXI4 and APB4 protocol compliant
• 1 to many connection (1 AXI master servicing several APB slaves)
• Configurable interface parameters:
  • address width
  • data width - any 2^n bits
  • burst length - up to 16 transfers
  • transaction ID width
  • user-defined signals width
• Buffer for configurable number of outstanding write and read AXI transactions
• Clock domain crossing (CDC) support - switchable
• APB data aggregation before accessing AXI bus for response channel

Benefits

• Configurable solution fully compliant with AMBA AXI4 and AMBA APB4 protocols
• Bug-free design coming with complete UVM verification environment and test suite
• FPGA proven

Deliverables

• Fully verified and FPGA-proven RTL written in Verilog
• Full-blown UVM/SV verification environment with UVCs and tests
• Full documentation - Datasheet, User Guide, Test Plan
• Full-fledged support from Vtool’s customization team

Technical Specifications