The MVD ASI Transmitter core is a drop-in module that includes the following functions :
• 188 or 204 bytes MPEG-TS input
• 8B/10B Coding
• Sync Byte (FC Comma) Insertion
• Parallel/Serial Conversion
• Output signal polarity: normal or inverted
ASI Transmitter
Overview
Key Features
- European standard EN50083-9 Annex B
- Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
- 135MHz Single clock
- Supports 188 or 204 bytes packet input
- Supports Data Packet or Data Burst format
- Choice of the output signal polarity
- Single channel – support for multi channel
- Full synthesizable RTL VHDL design (not delivered) for easy customization
Block Diagram
Applications
- ASI Transmitter may be used in applications related to DVB/MPEG-2 transport streams.
Deliverables
- Datasheet
- Netlist for core generation
- VHDL top file
- VHDL source code : can be delivered as an option under NDA and other specific clauses
Technical Specifications
Availability
Available